Capacitor over bit line memory cell and process

ABSTRACT

A stacked capacitor memory cell and method for its fabrication including providing a layer of insulation glass over word lines on a silicon semiconductor substrate; self-aligning contact holes at the storage nodes and bit line contact location; providing a blanket layer of polysilicon, then silicide, and then an insulating cap; removing a portion of the insulating cap, silicide and polysilicon to form polysilicon plugs having outward surfaces at an elevation below the surface of the insulating glass, thus forming the bit line, a bit line contact and isolating the storage nodes; and providing a stacked capacitor on top of the bit line and in electrical communication with the storage node contact location through the plugs formed simultaneously with the bit line and bit line contact.

This application is a divisional of application, Ser. No. 08/998,023 filed Dec. 24, 1997, now U.S. Pat. No. 6,060,351 the entirety of which is incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to capacitor over bit line structures for memory cells, such as dynamic random access memory (DRAM) cells, and to methods for fabricating such structures and cells.

2. Description of the Related Art

As memory cell density increases, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. One way of increasing cell capacitance is through three-dimensional cell capacitor structures, such as trenched or stacked capacitors.

Stacked capacitor DRAMs utilize either a buried bit line or a non-buried bit line structure. With buried bit line structures, bit lines are provided in close vertical proximity to the bit line contacts of the memory cell field effect transistors (FETs), and the cell capacitors are formed horizontally over the top of the word lines and bit lines. Buried bit line structures, sometimes referred to as capacitor-over-bit-line (COB) structures, are the subject of this invention.

Sim et al., “A New Planar Stacked Technology (PST) for Scaled and Embedded DRAMs,” IEEE, IEDM 96-597-600 (1996), refers to a COB type DRAM structure made by a process of inserting a connecting layer between a storage node contact and a gate polysilicon layer. After formation of a tungsten damascene bit line, the storage node contact is opened and a polysilicon plug is formed by deposition and etch-back. Capacitors are formed by oxide etch selective to storage node hole formation, followed by polysilicon deposition and CMP for cylindrical capacitor definition. The cell plate is then patterned, followed by W-plug CMP and metalization.

M. Sakao et al., “A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs,” IEEE, IEDM 90-655-658 (1990), refers to a process for making a COB cell wherein, after opening a self-aligned contact to the active area, a polysilicon layer is formed as a local interconnect. After an insulating interlayer deposition, a bit line contact is opened and filled with a doped polysilicon plug. A polycide bit line is then formed, and an insulating interlayer is deposited on the bit line and planarized. After opening the capacitor contact, an HSG polysilicon storage node is formed and connected to the active area through the capacitor contact and local interconnect.

The goal of increasing or, at least, maintaining cell capacitance as cell size shrinks must be attained without resorting to processes that increase the number of masking, deposition, etch and other steps in the production process. This has a great impact on manufacturing costs, particularly the costs of photolithographic steps. High capital costs are associated with photolithographic equipment and more complex photo processing, in terms of more photo process steps per level, more equipment, and the use of expensive ultra clean room floor space. Defect density is inevitably increased with each additional photomasking layer and compromises yield and reliability. All photo layers also require a subsequent step, either implant or etch. These additional steps further add to manufacturing costs.

What is needed is a capacitor over bit line cell of reduced complexity that can be fabricated with a minimum of process steps.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method for fabricating a buried bit line stacked-capacitor memory cell by a process that reduces the number of photomasking and etching steps.

A further object of the present invention is to provide a method for fabricating a buried bit line memory cell having a bit line, plugs for the future capacitors, and plugs of slots in the periphery for shallower contacts, which can all be formed in a single processing step.

Yet a further object of the present invention is to provide a DRAM cell with a stacked capacitor over silicided bit line structure having reduced complexity and thus reduced defect density, increased ease of manufacture, and reduced manufacturing cost.

These and other objects of the present invention are achieved by providing a method of forming a capacitor over bit line memory cell by:

providing an array of substantially electrically isolated word lines atop a semiconductor wafer;

providing active areas about the word lines to define an array of memory cell field effect transistors (FETs), the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line;

providing a first layer of electrically insulating material over the word lines and active regions, the layer of insulating material having an uppermost surface which is above the word lines;

providing first and second respective contact openings through the first insulating material layer to the first and second active regions;

providing a first layer of electrically conductive material over the first insulating material and within the first and second contact openings;

removing a portion of the first conductive material to outwardly expose remaining first insulating material, and to outwardly expose remaining first electrically conductive material within the first contact opening at an uppermost surface of said remaining first conductive material which is elevationally below the surface of the remaining first insulating material;

providing a second conductive layer and a bit line insulating material outwardly of the first layer of electrically conductive material;

providing a third layer of electrically conductive material having an uppermost surface above the bit line; and

removing a portion of the third electrically conductive layer selective to the underlying bit line insulating material to form a capacitor storage node.

In another embodiment the present invention provides a method of forming a capacitor over bit line memory cell by:

providing a silicon semiconductor substrate having a word line and an active area;

providing a first insulating material layer over the word line and active area;

opening first and second contact holes through the first insulating layer to a first contact location and a second contact location of the active area;

providing a first conductive material layer over the first insulating material and within the first and second contact holes;

removing a portion of the first conductive material layer to expose an outward surface of the conductive material at an elevation below the elevation of the outward surface of the first insulating material to form a bit line contact above the first contact location and an isolated conductive material plug above the second contact location; and

providing a capacitor atop the bit line contact and in electrical contact with the second active area through the plug.

According to another embodiment, the present invention provides a semiconductor processing method of forming a capacitor over bit line by:

providing a first and second opening in an insulating layer on a substrate;

providing an electrically conductive overlying layer to fill said first and second openings and form first and second electrically conductive pillars;

removing a portion of said first electrically conductive pillar to outwardly expose a surface of the first electrically conductive pillar which is elevationally below said insulating layer and second pillar;

capping said second pillar to form a bit line;

providing a second electrically conductive material over said bit line and in contact with said first pillar to form a capacitor storage node;

providing a dielectric layer over said storage node; and

providing an electrically conductive outer capacitor plate atop said dielectric layer.

In yet another embodiment, the present invention provides a stacked capacitor memory cell comprising a semiconductor substrate having word lines with an insulating material overlaying the substrate and word lines except at bit line contact and storage node contact locations of the substrate;

a polysilicon bit line contact and polysilicon storage node contact in electrical communication with respective active areas of the substrate, wherein the contacts are electrically isolated from each other by the insulating material;

a silicided bit line in electrical communication with said bit line contact;

a periphery polysilicon plug in electrical communication with the bit line; and

a capacitor above the bit line and in electrical communication with the storage node contact.

According to yet another embodiment, the present invention provides a stacked capacitor memory cell comprising a semiconductor substrate having word lines with an insulating material overlaying the substrate and word lines except at bit line contact and storage node contact locations of the substrate;

a polysilicon bit line contact and polysilicon storage node contact in electrical communication with respective active areas of the substrate, wherein said contacts are electrically isolated from each other by the insulating material;

a spacered and capped silicided bit line in electrical communication with the bit line contact;

a capacitor above the bit line and in electrical communication with the storage node contact, the capacitor comprising a dielectric and a hemispherical grain polysilicon material between the storage node and dielectric; and

wherein the cell further comprises slots for periphery contacts within the polysilicon material of the bit line contact; and wherein the slots for periphery contacts, the bit line contact, and the capacitor storage node all comprise polysilicon, and the slots for periphery contacts are in direct electrical communication with the bit line.

Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top plan layout of a stacked-cell DRAM array.

FIG. 1B is a schematic top plan layout of a single cell of the array of FIG. 1A. The subsequent drawing figures, which depict steps of the process of the invention, are cross-sectional views through locations of an in-process cell of the type shown by FIGS. 1A and 1B.

FIG. 2 is a sectional view of the semiconductor wafer fragment of FIG. 1B along section III at one processing step in accordance with the invention.

FIG. 3 is a view of the FIG. 2 wafer taken at a step subsequent to that shown by FIG. 2.

FIG. 4 is a view of the FIG. 2 wafer taken at a step subsequent to that shown by FIG. 3.

FIG. 5 is a view of the FIG. 2 wafer taken at a step subsequent to that shown by FIG. 4.

FIGS. 6A and 6B are cross-sectional views of the in-process array through broken lines I and II, respectively, of FIG. 1A at the same step shown by FIG. 5.

FIG. 6C is a view of the FIG. 2 wafer taken at a step subsequent to that shown by FIG. 5.

FIG. 7 is a view of the FIG. 6B wafer taken at a step subsequent to that shown by FIG. 6B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIGS. 1A and 1B, a top plan layout of a completed stacked-cell DRAM array is depicted. The present invention, will be described in the context of the fabrication of an array having the same top plan layout as that depicted in FIGS. 1A and 1B. The subsequent figures, which depict steps of the process at various stages, are cross-sectional views taken at locations within the array represented as broken lines I, II, and III. The figures are not meant to be actual cross-sectional views of any particular portion of a real DRAM cell, but are merely convenient tools employed to more fully depict the process aspect of the invention at various stages of manufacture.

The completed stacked-cell DRAM array is fabricated on a silicon semiconductive substrate 10, typically a silicon semiconductive material. The term “substrate” herein shall be understood to mean one or more semiconductive layers or structures which include active or operable portions of semiconductor devices. A series of substantially parallel, spaced apart, polysilicon word lines 11, silicided with tungsten, titanium, or other refractory metal, traverses substrate 10, in which have been created a plurality of active areas 12 (the square S-shaped regions) which are insulated from one another by field oxide regions (not shown in this view). Each active area 12, which corresponds to the domain of a single memory cell, contains a storage node contact region 13 where that cell's storage node capacitor plate makes contact to the substrate within the cell's domain. Each cell domain has a single bit line contact region 14. Each of the substantially parallel, spaced-apart bit lines 15 makes contact with a plurality of bit line contact regions 14. Eventually, the bit lines and word lines will be connected to periphery contacts (not shown), which are located at the respective ends of the array and are capable of being in electrical communication with peripheral circuitry.

Referring to FIG. 2, a semiconductor wafer fragment is indicated generally by reference numeral 16. Wafer 16 is defined in part by silicon semiconductive substrate 10, and an array of substantially electrically isolated word lines, such as the illustrated word lines 17, 18 and 19. Such word lines have a lowermost gate oxide layer 20, a lower polysilicon layer 21, an overlying silicide layer 22 such as tungsten silicide, an insulating cap 23, and side insulating spacers 24. Spacers 24 and caps 23 preferably comprise an insulative nitride, such as Si₃N₄. A thin barrier layer 25 of Si₃N₄ (or, more preferably, tetraethylorthosilicate glass, TEOS) may be provided atop the wafer to function as a diffusion barrier. Layer 25 has a thickness which is preferably about 200 Angstroms to about 300 Angstroms when TEOS, and about 100 Angstroms to about 250 Angstroms when Si₃N₄.

Active regions are provided about the word lines, such as active regions 26, 27 and 28, to define an array of memory cell FETs. The discussion below proceeds with reference to an FET formed using word line 18, which will be provided with a capacitor construction for a single memory cell. Active region 28 will define a first active region for electrical connection with a memory cell capacitor. Active region 27 will define a second active region for electrical connection with a bit line. Field oxide 29 is provided, as shown.

Referring still to FIG. 2, a first insulating material layer 30 is blanket deposited over the word line 18 and active areas 27, 28, as shown. Preferred insulating materials for layer 30 are oxides, most preferably borophosphosilicate glass (BPSG). The deposition thickness of layer 30 is typically about 10,000 Angstroms. Layer 30 is preferably reflowed by heating to its glass transition temperature to densify the BPSG, and then polished to make a planarized surface.

Referring to FIG. 3, a series of first contact openings 31 and second contact openings 32 are provided through first insulating material layer 30 to first and second active regions 28 and 27, respectively. Such openings would typically be formed by photomasking and dry etching of BPSG selectively relative to the nitride of the word line caps 23. An example etch chemistry would include CHF₃ and O₂ at low O₂ flow rate (i.e., less than 5% O₂ by volume in a CHF₃/O₂ mixture), or the combination of CF₄, Ar, CH₂F₂ and CHF₃. The principal purpose of optional barrier layer 25 is to minimize diffusion of boron or phosphorus atoms from BPSG layer 30 into active areas 27 and 28. Word line caps 23 are preferably comprised of nitride (Si₃N₄) and layer 30 is comprised of oxide, such that the etch to produce first contact openings 31 and 32 will stop relative to word line spacers 24 and caps 23.

Referring to FIG. 4, the series of contact openings 31 and 32 are filled with a blanket deposition of a conductive material 33, preferably polysilicon, to a level above the outermost surface of the first insulating layer 30. A blanket silicide layer 34 (preferably WSi_(x)) is then applied continuously over the wafer on top of the conductive material 33. An insulating cap 35 is then layered on top of the silicide layer 34. The thickness of layers 33, 34 and 35 is typically about 3000, 1200 (or more), and 1900 Angstroms, respectively.

As an alternative to polysilicon for conductive layer 33, a metal may be used together with a barrier film. This is accomplished using one of several well-known techniques, such as depositing or sputtering a refractory metal silicide layer such as WSi_(x) directly, or depositing a refractory metal (e.g. tungsten, titanium, or cobalt) layer on top of a first polysilicon layer and, then, annealing so that it reacts with the underlying polysilicon to form the silicide. In order to prevent the refractory metal silicide layer from separating from the first polysilicon layer during subsequent elevated temperature cycles, an optional silicon dioxide capping layer is deposited on top of silicide layer 34, following which an optional silicon nitride capping layer may be deposited on the top of the oxide capping layer.

Referring to FIG. 5, the area defined as the bit line is masked with photoresist. The unmasked polysilicon conductive material layer 33, silicide (WSi_(x)) layer 34 and insulating cap layer 35 are etched back to remove them from over the insulating material 30. The polysilicon 33, silicide 34 and capping layer 35, which remain after the removal (etch), define bit line 36. In addition to forming bit line 36, the removal process isolates the future storage nodes, i.e., electrically conductive materials within the first 28, and second 27, contact areas are isolated because electrically conductive material 33 is etched back to an elevation that is below the outermost surface of the insulating material (BPSG) 30. The electrically conductive (polysilicon) material 33 remaining within contact area 28 defines a conductive plug for the capacitor to contact the active area of the substrate. The electrically conductive material 33 within contact area 27 defines a bit line contact for bit line 36, and can also be readily employed for slots in the periphery for shallower contacts (not shown). Accordingly, it is now apparent that the process of the present invention advantageously allows for the formation of three or more key structural features by a single masking and conductive material removal step; in addition, the bit line contact, plugs for the future capacitor, and plugs in the periphery, may all be formed by the same conductive material 33 in a single conductive material deposition step.

Referring still to FIG. 5, and as also shown from a different perspective by FIGS. 6A and 6B, the bit line 36 is then spacered with either oxide or nitride by depositing insulator spacer material 37, preferably silicon nitride (Si₃N₄), over the entire surface. Spacer oxide or nitride material 37 is preferably deposited by chemical vapor deposition (CVD), to a thickness of about 300 to 1500 Angstroms. Spacer material 37 is then removed with anisotropic etch, leaving only shoulders of spacer material 37 on the vertical surfaces of bit line 36.

FIG. 6A is a section along hatched line I of FIG. 1A and shows bit line 36 and bit contact 14, between a series of word lines 11 (FIGS. 1A and 6A), connecting bit line 36 to active area 12 of semiconductor substrate 10. Silicide layer 34, preferably WSi_(x), forms a continuous planarized layer atop conductive material 33, and insulating cap layer 35, an oxide, forms a continuous planarized layer atop silicide layer 34, of bit line 36. FIG. 6B is a section along hatched line II of FIG. 1A and shows bit lines 36 including spacer material 37, and bit contact 14 to active area 12 of substrate 10; the hatched horizontal lines in FIG. 6B depict the gate oxide layer 20, polysilicon layer 21, silicide layer 22 and insulating caps 23 of word line 11 (FIGS. 1A and 6B).

At the in-process stage of the wafer fragments depicted in FIGS. 5 and 6, the silicided bit line is now formed, substantially simultaneously with formation of the conductive plugs for the future capacitors, as well as isolation of the capacitor storage nodes. FIG. 6C shows the wafer fragments of FIGS. 5 and 6 (A and B) after formation of a local interconnect 46. FIG. 6C also shows slot for periphery plug contact 45. Various capacitor structures can be formed atop the bit line and in electrical communication with the capacitor plugs by various capacitor fabrication techniques, including but not limited to, the capacitor block structure described below and depicted in FIG. 7.

Referring to FIG. 7, a polysilicon layer 38 is deposited. An optional rough layer 39 of rugged polysilicon, for example, hemispherical grain polysilicon (HSG), is then deposited atop layer 38 to increase surface area for improved capacitance. The preferred rugged polysilicon is combo HSG (CHSG) which is typically deposited by LPCVD to a thickness of from 300 to 1000 Angstroms. Islands are then formed by masking the capacitor areas, and polysilicon layer 38 is etched selective to the underlying spacer material 37, thus forming the lower capacitor plate (storage node) blocks 40 for the capacitors.

Next, a thin dielectric material layer 41, preferably Si₃N₄ or Ta₂O₅, is deposited over the capacitor storage nodes 40, and conductive outer layer (cell plate layer) 42 is then blanket deposited atop dielectric 41. The dielectric layer may typically have a thickness of about 25 to 150 Angstroms. Various suitable dielectric materials and combinations of these may be employed. Cell plate 42 is deposited thickly enough (preferably, 300 to 2000 Angstroms) to fill gaps between cells in order to make a planar surface 43.

Thus, a stacked capacitor DRAM cell is provided with a silicided bit line 36 formed while forming plugs 44 for the future capacitors, as well as plugs of slots 45 in the periphery for shallower contacts. The spacering of the bit line 36 allows for capacitor block etch to be selective to spacers 37. Various other capacitor structures and fabrication steps may be employed to form capacitors over bit line 36 and in contact with plugs 44. Although the process was depicted with reference to a block capacitor process flow, it may be easily adapted to a process utilizing container, cylindrical, double cylindrical, crown shaped, ring or vertical fin capacitors, as shown for example in U.S. Pat. No. 5,270,241. Such capacitors can be constructed in accordance with known processing techniques by one of ordinary skill in the art, given the capacitor plug and buried bit line processing techniques taught herein. For example, polysilicon layer 38 may be masked and etched to form a cylindrical capacitor with optional rugged polysilicon layer 39 then deposited on the sides, as opposed to the top surface, of the remaining polysilicon 38.

Finally, insulator glass is deposited, and a suitable back end metalization process such as a CMP-based process is used to connect up the devices. The array may now be completed using processing techniques that are well known in the art, including opening holes in the overlaying insulator glass to the polysilicon periphery plugs, metalizing the holes via tungston plugs or aluminum force fill, and then patterning and etching conductive lines on the surface to form local interconnects 46 (FIG. 6C). Although only a single embodiment of the process has been disclosed herein, it will be obvious to those having ordinary skill in the art that changes and modifications may be made to the process without departing from the scope and spirit of the invention as claimed. For example, the process of the invention may be performed to fabricate arrays having straight-line, as opposed to the S-shaped, active areas shown in FIGS. 1A and 1B. Similarly, other dielectric materials such as silicon dioxide, titanium oxide, yttrium oxide, barium strontium titanate, combinations of these, and others, may be used for dielectric 41, and other insulating materials, such as the above and various other oxides, may be substituted for the BPSG of layer 30. Additionally, materials other than HSG or CHSG (e.g., cylindrical grain poly (CGP)) may be substituted for rugged polysilicon layer 39.

Accordingly, it is to be understood that although the present invention has been described with reference to a preferred embodiment, various modifications, known to those skilled in the art, may be made to the structures and process steps presented herein without departing from the invention which is defined in the claims appended hereto. 

We claim:
 1. A stacked capacitor memory cell comprising: a semiconductor substrate having word lines with an insulating material overlaying the substrate and word lines except at bit line contact and storage node contact locations of the substrate; a polysilicon bit line contact and polysilicon storage node contact in electrical communication with respective active areas of the substrate, wherein said contacts are electrically isolated from each other by the insulating material; a silicided bit line in electrical communication with said bit line contact; a periphery polysilicon plug in electrical communication with said bit line; and a capacitor above the bit line and in electrical communication with said storage node contact.
 2. The cell of claim 1 comprising insulating cap and side spacers on said bit line.
 3. The cell of claim 1 wherein said capacitor comprises a dielectric and a rugged polysilicon material between said storage node and dielectric.
 4. The cell of claim 1 comprising slots for periphery contacts within the polysilicon material of said bit line contact.
 5. The cell of claim 4 wherein said slots for periphery contacts, said bit line contact and said capacitor storage node comprise substantially one material.
 6. The cell of claim 5 wherein said one material is polysilicon.
 7. The cell of claim 3 wherein said capacitor further comprises a cell plate, and an overlaying insulating glass layer.
 8. The cell of claim 7 further comprising openings through said overlaying glass to the periphery contacts, wherein said openings are filled with a metal to form a metal plug.
 9. The cell of claim 8 wherein said metal is selected from the group consisting of tungsten and aluminum.
 10. The cell of claim 8 further comprising electrically conductive interconnecting lines on the surface of the insulating glass and in electrical communication with said metal plug.
 11. A stacked capacitor memory cell comprising: a semiconductor substrate having word lines with an insulating material overlaying the substrate and word lines except at bit line contact and storage node contact locations of the substrate; a polysilicon bit line contact and polysilicon storage node contact in electrical communication with respective active areas of the substrate, wherein said contacts are electrically isolated from each other by the insulating material; a spacered and capped silicided bit line in electrical communication with said bit line contact; and a capacitor above the bit line and in electrical communication with said storage node contact, said capacitor comprising a dielectric and a rugged polysilicon material between said storage node and dielectric; wherein said cell further comprises slots for periphery contacts within the polysilicon material of said bit line contact, said slots for periphery contacts, said bit line contact, and said capacitor storage node comprising polysilicon, and said periphery contacts being in direct electrical communication with said bit line. 